For an active matrix type liquid crystal display device, an auxiliary capacitance is added to a liquid crystal capacitance for achieving stability of a charge held in a picture element.
FIG. 12 is a plan view illustrating an example of a structure of a picture element, to which the auxiliary capacitance is to be added. In this structure, one picture element includes two sub picture elements. Such a structure of the picture element is described, for example, in Patent Literature 1.
A picture element PIXjk, which is driven by a j-th gate bus line GLj and a k-th source bus line SLk, includes a sub picture element P1 and a sub picture element P2 that are disposed symmetrically with respect to the gate bus line GLj, and along a direction that the source bus line SLk extends toward the gate bus line GLj. Here, a sub picture element positioned on a gate bus line GLj-1 side with respect to the gate bus line GLj is referred to as the sub picture element P1, whereas a sub picture element positioned on a gate bus line GLj+1 side with respect to the gate bus line GLj is referred to as the sub picture element P2. The sub picture element P1 includes a TFT 114(1), and the sub picture element P2 includes a TFT 114(2).
The TFT 114(1) includes a gate electrode 114(1)g which is connected to the gate bus line GLj, and a source electrode 114(1)s which is connected to the source bus line SLk. The TFT 114(1) further includes a drain electrode 114(1)d, which is connected to a picture element electrode 109 of the sub picture element P1 through a contact hole 111 provided above the drain electrode 114(1)d. The TFT 114(2) includes a gate electrode 114(2)g which is connected to the gate bus line GLj, and a source electrode 114(2)s which is connected to the source bus line SLk. The TFT114(2) further includes a drain electrode 114(2)d, which is connected to the picture element electrode 109 of the sub picture element P2 through the contact hole 111 provided above the drain electrode 114(2)d. 
Further, an auxiliary capacitor bus line CSLj+1 is provided between the gate bus line GLj and the gate bus line GLj+1 so that the auxiliary capacitor bus line CSLj+1 extends parallel to the gate bus line GLj and the gate bus line GLj+1. In the sub picture element P2 of the picture element PIXjk, the picture element electrode 109 has an edge section facing toward the gate bus line GLj+1 and this edge overlaps with the auxiliary capacitor bus line CSLj+1 so as to form an auxiliary capacitor Cs2 therebetween. Furthermore, in a sub picture element P1 of a picture element PIX(j+1)k, the picture element electrode 109 has an edge section facing toward the gate bus line GLj and this edge section overlaps with the auxiliary capacitor bus line CSLj+1 so as to form an auxiliary capacitor Cs1 therebetween. Similarly, in a sub picture element P1 of the picture element PIXjk, the picture element electrode 109 has an edge section facing toward a gate bus line GLj-1 (not illustrated) and this edge section overlaps with an auxiliary capacitor bus line CSLj (not illustrated) so as to form an auxiliary capacitor Cs1 therebetween. The other sub picture elements are similarly configured.
FIG. 13 illustrates an equivalent circuit of the structure of the picture element of FIG. 12. The sub picture element P1 of each picture element includes a capacitor constituted from a liquid crystal capacitor CL1 and the auxiliary capacitor Cs1, whereas the sub picture element P2 of each picture element includes a capacitor constituted from a liquid crystal capacitor CL2 and the auxiliary capacitor Cs2. The liquid crystal capacitor CL1 and the liquid crystal capacitor CL2 are respectively formed between (i) the picture element electrode 109 of the sub picture element to which the liquid crystal capacitor CL1 or the liquid crystal capacitor CL2 belongs and (ii) a common electrode to which a voltage Vcom is applied.
The picture element PIXjk is configured such that the TFT114(1) and the TFT114(2) become conductive at the same time when a selective voltage is applied to the gate bus line GLj. At this point, a voltage of a data signal being supplied to the source bus line SLk is written to the picture element electrode 109 of each of the sub picture elements P1 and P2. The auxiliary capacitor bus line CSLj and the auxiliary capacitor bus line CSLj+1 are driven by, for example, binary voltages in opposite phases. Accordingly, even if the same data signal is supplied from the source bus line SLk to the sub picture elements P1 and P2, each of the liquid crystal capacitors CL1 and CL2 applies a different voltage to a liquid crystal layer. As a result, it is possible for each of the sub picture elements P1 and P2 to achieve different display brightness, thereby achieving excellent visual characteristics of the picture element PIXjk as a whole.
FIG. 14 is a cross-sectional view taken along the line A-A′ of FIG. 12. Patterned on a transparent substrate 101 are the gate electrode 114(2)g of the TFT 114(2), the auxiliary capacitor bus line CSLj+1, and a gap adjusting layer 102, each of which is made of a gate metal layer that is a laminate film of Ti/Al/Ti. Further, although not illustrated, the gate bus line GLj is also patterned on the transparent substrate 101 by using the gate metal layer. Then, on these patterns, a gate insulating film 103 is formed so that the patterns are covered with the gate insulating film 103. Above the gate electrode 114(2)g, a semiconductor layer 104 made of an intrinsic semiconductor layer (i-layer) and a semiconductor layer 105 made of a silicon n+ layer (ohmic contact layer) are stacked in this order on the gate insulating film 103 in positions each of which corresponds to a source region and a drain region. Further, formed on the semiconductor layers 104 and 105 so as to cover the semiconductor layers 104 and 105 are: the source bus line SLk, the source electrode 114(2)s, and the drain electrode 114(2)d, each of which is made of a source metal formed by stacking a first source metal layer 106 made of Ti and a second source metal layer 107 made of Al in this order. The drain electrode 114(2)d is provided so that it reaches a position above the gap adjusting layer 102.
Furthermore, a passivation film 108 made of SiNx is formed so that the passivation film 108 covers the substrate on which the source electrode 114(2)s and the drain electrode 114(2)d are formed. Formed on the passivation film 108 is the picture element electrode 109 made of an ITO (transparent electrode). The picture element electrode 109 is connected to the drain electrode 114(2)d through the contact hole 111 formed on the passivation film 108. The contact hole 111 includes an etching aperture of the drain electrode 114(2)d and a through hole formed on the gate insulating film 103, and reaches a top surface of the gap adjusting layer 102. As such, the picture element electrode 109 makes contact also with the top surface of the gap adjusting layer 102.
The auxiliary capacitor bus line CSLj+1 overlaps the picture element electrode 109 so as to form the auxiliary capacitor Cs2. Here, the auxiliary capacitor Cs2 is a capacitor CGI+PAS, whose dielectric material is a laminate film made of the gate insulating film (GI) 103 and an interlayer insulating film (PAS) 108.
Next, a manufacturing process of the structure of FIG. 14 is described with reference to FIGS. 15 and 16. It should be noted that the transparent substrate 101 is not illustrated in FIGS. 15 and 16.
First in step 1, as shown in (a) of FIG. 15, the gate metal layer GM made of the laminate film of Ti/Al/Ti is formed on the transparent substrate 101 by sputtering. Next in step 2, as shown in (b) of FIG. 15, a photoresist is patterned so that it remains on a part of the gate metal layer GM, which part is desired to remain on the transparent substrate 101. Here, the photoresist is patterned by performing exposure, development, and post-bake in this order (the photoresist is patterned in this manner also in the after-described processing steps). Then, by using the photoresist as an etching mask, the gate metal layer GM is wet-etched with etchant containing a mixture solution of hydrofluoric acid and nitric acid, a mixture solution of hydrofluoric acid and hydrogen peroxide, or the like, thereby forming the gate electrode 114(2)g, the auxiliary capacitor bus line CSLj+1, and the gap adjusting layer 102. Such a wet etching method may be selected from methods described in Patent Literatures 3 to 7, by which methods a Ti alloy or a metal containing Ti is etched. Since such methods have a high etching rate, etching uniformity is preferably increased by, for example, stirring the etchant or spraying the etchant. Further, an often-used etching method other than the wet etching method is a dry etching method, in which a reactive ion etching using chlorine gas is performed.
Next in step 3, as shown in (c) of FIG. 15, the gate insulating film 103 is formed. On the gate insulating film 103, the intrinsic semiconductor layer, which will become the semiconductor layer 104, and the n+ silicon layer, which will become the semiconductor layer 105, are grown in succession. Then in step 4, as shown in (d) of FIG. 15, the photoresist is patterned. By using the photoresist as the etching mask, the silicon n+ layer and the intrinsic semiconductor layer are etched so as to form (i) the semiconductor layer 104 and (ii) the semiconductor layer 105 which is not yet separated into the source region and the drain region. Subsequently in step 5, as shown in (e) of FIG. 15, a Ti film, which will become the first source metal layer 106, and an Al film, which will become the second source metal layer 107, are formed all over by sputtering, and thereafter, the photoresists are patterned so as to form the source bus line SLk and to separate the source region and the drain region of the TFT 114(2). In performing this patterning, it is necessary to also form an etching window in a region on which the contact hole 111 is to be formed. In this regard, since there is the gap adjusting layer 102 provided beneath the region on which the contact hole 111 is to be formed, it is possible to pattern the etching window in the substantially same plane as the other patterns. Further, the gap adjusting layer 102 makes it possible to stop the etching at the Ti film formed on a top surface of the gap adjusting layer 102 by utilizing a difference in etching rate, in a case where the contact hole 111 is made deeper to the gate insulating film 103.
Then in step 6, as shown in (a) of FIG. 16, by using the photoresists as the etching masks, the Al film is etched selectively against the Ti film with phosphoric acid or the like. Next in step 7, as shown in (b) of FIG. 16, by using the above photoresists as the etching masks, the Ti film is dry-etched by the reactive ion etching using the chlorine gas. Here, in the TFT 114(2) region, the n+ silicon layer is also etched at the same time. As a result, the first source metal layer 106 and the second source metal layer 107 are formed, thereby obtaining the source bus line SLk, the source electrode 114(2)s, and the drain electrode 114(2)d. 
Next in step 8, as shown in (c) of FIG. 16, the passivation film 108 is formed all over by CVD, and the photoresist is patterned so as to form the contact hole 111. Further in step 9, as shown in (d) of FIG. 16, the passivation film 108 and the gate insulation film 103 are dry-etched by the reactive ion etching using the chlorine gas. As a result, the contact hole 111 is formed. Then in step 10, as shown in (e) of FIG. 16, the picture element electrode 109 is formed on the passivation film 108 and on an inner surface of the contact hole 111.
Furthermore, Patent Literature 2 also discloses the same structure.
Citation List
Patent Literature 1
Japanese Patent Application Publication, Tokukai, No. 2004-62146 A (Publication Date: Feb. 26, 2004)
Patent Literature 2
Japanese Patent Application Publication, Tokukai, No. 2005-242306 A (Publication Date: Sep. 8, 2005)
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Japanese Patent Application Publication, Tokukai, No. 2005-320608 A (Publication Date: Nov. 17, 2005)
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